$$\begin{array}{l}
计算cache指引大小: \\
2^{index}=\frac{Cache \ size}{Block \ size \times Set \ associativity} \ {\color{Red} 1} \\
CPU \ execution \ time = (CPU \ clock \ cycles + Memory \ stall \ cycles) \times Clock \ cycle \ time \ {\color{Red} 2} \\
\begin{aligned}
Memory \ stall \ cycles &= Number \ of \ misses \times Miss \ penalty \ {\color{Red} 3} \\
&= IC \times \frac{Misses}{Instruction} \times Miss \ penalty \ {\color{Red} 4}
\end{aligned} \\
\frac{Misses}{Instruction}=Miss \ rate \times \frac{Memory \ accesses}{Instruction} \ {\color{Red} 5} \\
Average \ memory \ access \ time=Hit \ time + Miss \ rate \times Miss \ penalty \ {\color{Red} 6}
\end{array}$$

$$\begin{aligned}
CPU \ execution \ time &= IC \times (CPI_{execution} + \frac{Memory \ stall \ clock \ cycles}{Instruction}） \times Clock \ cycle \ time \ {\color{Red} 7} \\
&=IC \times (CPI_{execution} + \frac{Misses}{Instruction} \times Miss \ penalty) \times Clock \ cycle \ time \ {\color{Red} 8} \\
&=IC \times (CPI_{execution} + MIss \ rate \times \frac{Memory \ access}{Instruction} \times Miss \ penalty) \times Clock \ cycle \ time \ {\color{Red} 9}
\end{aligned}$$

乱序执行处理器

$$
\begin{aligned}
\frac{Memory \ stall \ cycles}{Instruuction} = \frac{Misses}{Instruction} \times (Total \ miss \ latency – Overlapped \ miss \ latency) \ {\color{Red} {10}}
\end{aligned}
$$

多层次缓存

$$\begin{array}{l}
Average \ memory \ access \ time = Hit \ time_{L1}+Miss \ rate_{L1} \times (Hit \ time_{L2} + Miss \ rate_{L2} \times Miss \ penalty_{L2}) \ {\color{Red} {11}}
\end{array}$$

$$\begin{array}{l}
\frac{Memory \ stall \ cycles}{Instruction} = \frac{Misses_{L1}}{Instruction} \times Hit \ time_{L2} + \frac{Misses_{L2}}{Instruction} \times Miss \ penalty_{L2} \ {\color{Red} {12}}
\end{array}$$

解释一下

等式1求出了cache的索引大小，之前说过几路组相联就是将几个block相联起来，所以总的cache大小除以单个block大小和一个相联有几个block数，最终求出cache的索引大小

等式2CPU的执行时间等于CPU的时钟周期加上Memory停顿周期，最终乘以单个时钟周期时间

等式3、4求memory停顿周期，首先等式3给出memory停顿周期为未命中数乘以未命中的惩罚周期。等式4为指令总数乘以单个指令的未命中数乘以未命中惩罚周期

等式5求单个指令的未命中数为未命中几率乘以单个指令的访存数

等式6给出平均内存访问期望时间为命中时间加上未命中几率乘以未命中惩罚周期

等式7、8、9将以上等式汇总，CPI(clock per Instruction)指的是每个指令所花时钟周期数，所以很容易得到\( CPU \ clock \ cycles = IC(Instruction \ count) \times CPI(clock \ per \ Instruction) \)，将等式5带入等式4，可以得到\( Memory \ stall \ cycles = IC \times Miss \ rate \times \frac{Memory \ accesses}{Instruction} \times Miss \ penalty \)，将这两个等式代入等式2并且结合一下即可得到等式9

等式10解释当为乱序执行处理器时，需要将一些重叠的花费时间去掉

等式11解释当为两层存储器时的平均内存访问期望时间，变的地方也就是原本未命中惩罚变为L2的命中时间加上L2的未命中几率乘以L2的未命中惩罚，当L1未命中时，会从L2查找

等式12同等式11一样，原本L1的未命中惩罚细分为L2的命中和未命中情况